Methods of forming semiconductor constructions

ABSTRACT

The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying subs regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

TECHNICAL FIELD

[0001] The invention pertains to semiconductor constructions and methodsof forming semiconductor constructions. In particular aspects, theinvention pertains to methods of forming DRAM constructions.

BACKGROUND OF THE INVENTION

[0002] Electrical isolation is commonly utilized in semiconductorconstructions to alleviate, or prevent, leakage between electricaldevices. For instance, it is frequently desired in dynamic random accessmemory (DRAM) fabrication to avoid sub-threshold leakage between accessdevices (such as, for example, access transistor constructions). Therecan be several facets which influence leakage currents between fieldeffect transistor devices, including, for example, junction leakage insource/drain regions; drain-induced barrier lowering (DIBL) due to shortgate lengths; gate-induced drain leakage (GIDL) due to high electricfields in a gate overlap region; narrow-width effects; andstress-induced leakage current (SILC) due to a proximity of an isolationregion to a device.

[0003] A ratio of I_(on) (drive current) to I_(off) (sub-thresholdleakage) can be utilized as a figure of merit for determining if accessdevices are performing adequately. It is found that reducing gate oxidethickness of access devices can improve a sub-threshold behavior of thedevices while simultaneously increasing a drive current. However, athreshold voltage of a device reduces with the decrease in gate oxidethickness. Increasing dopant levels in channels of the devices canincrease the threshold voltage to an acceptable level and compensate forthe reduction in gate oxide thickness, but can increase junction leakagein source/drain regions. Additionally, the increased dopant level in achannel of a device can adversely cause junction capacitance toincrease, cause channel mobility reduction, and reduce the current driveof the device.

[0004] It would be desirable to develop new methods for reducingsub-threshold leakage of devices. It would be further desirable if suchnew methods avoided increasing dopant concentration in channel regionsof access devices. Additionally, it would be desirable if such newmethods could be utilized for forming structures suitable for electricalisolation in an integrated circuit construction.

SUMMARY OF THE INVENTION

[0005] In one aspect, the invention encompasses a semiconductorconstruction having a pair of channel regions within a semiconductorsubstrate. Each of the channel regions has a sub-region which is dopedwith indium or heavy atom acceptor atoms such as Ga or TI. The channelalso contains boron surrounding the sub-region. A pair of transistorconstructions is disposed over the semiconductor substrate, each of thetransistor constructions is disposed over one of the channel regions.The pair of transistor constructions is separated by an isolation regionwhich isolates the transistor constructions from one another. Eachtransistor construction has a transistor gate that is substantiallylaterally centered over the corresponding channel region. Each of thegates is wider than the underlying indium doped sub-region.

[0006] In one aspect, the invention encompasses a semiconductorconstruction having a first and a second transistor construction over asemiconductive substrate material. Each of the first and secondtransistor constructions has opposing sidewalls and a pair of insulativespacers along the sidewalls. The first transistor construction isdisposed between a first and a second source/drain region within thesubstrate. A first end of the first source/drain region extends beneaththe spacer on a first side of the first transistor construction and thesecond source/drain region extends beneath the spacer on an opposingsecond side of the first transistor construction. The second transistorconstruction is disposed between a third and a fourth source/drainregion within the substrate. A first side of the fourth source/drainregion extends beneath the spacer on a first side of the secondtransistor construction. The third source/drain region extends beneaththe spacer on an opposing second side of the second transistorconstruction. The first, second, third and fourth source/drain regionsare commonly doped with a first type of dopant. A source/drain extensionwhich is doped with a second type of dopant is associated with the firstside of the first source/drain region and extends the first side of thefirst source/drain region farther beneath the first transistorconstruction. Source/drain extensions are absent from a second side ofthe first source/drain region and are also absent from the secondsource/drain region.

[0007] The invention also encompasses methods of forming semiconductorconstructions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0009]FIG. 1 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction which can be formed in particularembodiments of the present invention.

[0010]FIG. 2 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction at a preliminary stage of a fabricationsequence which can be utilized in forming the FIG. 1 structure.

[0011]FIG. 3 is a view of the FIG. 2 wafer fragment shown at aprocessing stage subsequent to that of FIG. 2.

[0012]FIG. 4 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 3.

[0013]FIG. 5 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 4.

[0014]FIG. 6 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 5.

[0015]FIG. 7 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 6.

[0016]FIG. 8 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 7.

[0017]FIG. 9 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 8.

[0018]FIG. 10 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 9.

[0019]FIG. 11 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 10.

[0020]FIG. 12 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 11.

[0021]FIG. 13 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 12.

[0022]FIG. 14 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction which can be formed in a secondembodiment of the present invention.

[0023]FIG. 15 is a view of the FIG. 2 wafer fragment shown at analternate processing stage subsequent to that of FIG. 2.

[0024]FIG. 16 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 15.

[0025]FIG. 17 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 16.

[0026]FIG. 18 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 17.

[0027]FIG. 19 is a view of the FIG. 2 fragment shown at a processingstep subsequent to that of FIG. 18.

[0028]FIG. 20 is a view of the FIG. 2 fragment shown at a processingstage subsequent to that of FIG. 19.

[0029]FIG. 21 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction which can be formed in a thirdembodiment of the present invention.

[0030]FIG. 22 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction which can be formed in a fourthembodiment of the present invention.

[0031]FIG. 23 is a view of the FIG. 2 fragment shown at an alternativeprocessing stage of a construction similar to that shown in FIG. 14.

[0032]FIG. 24 is a view of the FIG. 2 fragment shown at a processingstep subsequent to that of FIG. 23.

[0033]FIG. 25 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction which can be formed in a fifthembodiment of the present invention.

[0034]FIG. 26 is a diagrammatic, cross-sectional view of a fragment of asemiconductor wafer construction at a preliminary stage of a fabricationsequence according to an alternative embodiment of the presentinvention.

[0035]FIG. 27 is a view of the FIG. 26 wafer fragment shown at aprocessing stage subsequent to that of FIG. 26.

[0036]FIG. 28 is a view of the FIG. 26 fragment shown at a processingstage subsequent to that of FIG. 27.

[0037]FIG. 29 is a view of the FIG. 26 fragment shown at a processingstage subsequent to that of FIG. 28.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038]FIG. 1 illustrates a semiconductor construction 10 encompassed byparticular aspects of the present invention. Construction 10 comprises asubstrate 12. To aid in interpretation of the claims that follow, theterms “semiconductive substrate” and “semiconductor substrate” aredefined to mean any construction comprising semiconductive material,including, but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0039] In particular aspects, construction 10 can correspond to a DRAMarray. Construction 10 comprises a pair of field effect transistordevices 14 and 16 supported by substrate 12, and also comprises a device38 having a different threshold voltage than devices 14 and 16. Device38 can be utilized for electrically isolating devices 14 and 16 from oneanother as discussed below.

[0040] Each of devices 14 and 16 comprises a transistor gate stack 22which includes an insulative material 24, a conductively dopedsemiconductive material 26 (also referred to as a gate layer), anelectrically conductive mass 28, and an insulative cap 30.

[0041] Insulative material 24 can comprise, for example, one or more ofsilicon nitride, silicon dioxide and silicon oxynitride. Insulativematerial 24 typically comprises silicon dioxide, and can be referred toas gate oxide.

[0042] Conductively-doped material 26 can comprise, for example,conductively-doped silicon. The silicon is typically in an amorphousand/or polycrystalline form. The dopant can comprise n-type dopant (suchas, for example, phosphorous or arsenic), or can comprise p-type dopant(such as, for example, boron).

[0043] Conductive mass 28 will typically comprise a layer of silicideformed directly on an upper surface of a silicon material 26; or a layerof metal formed directly on (i.e. physically against) a barrier layer ofWN_(x) or TiN, which in turn is on the silicon material 26.

[0044] Insulative cap 30 can comprise, for example, one or both ofsilicon nitride and silicon dioxide.

[0045] The gate stacks comprise sidewalls, and electrically insulativespacers 32 are formed along such sidewalls. Spacers 32 can comprise, forexample, silicon nitride, and can be formed by depositing a materialconformally over substrate 12 and gate stacks 22, and subsequentlyanisotropically etching such material.

[0046] A plurality of source/drain regions 34 are provided withinsubstrate 12 and between gate stacks 22. Gate stacks 22 can beconsidered as being directly over segments of substrate 12, andsource/drain regions 34 can be considered as being spaced from oneanother by at least portions of such segments. In the shownconstructions, source/drain regions 34 extend the entire spacer widthunder spacers 32.

[0047] Source/drain regions 34 are conductively-doped diffusion regionsextending into substrate 12. Typically, transistor constructions 14 and16 will be NMOS transistors, and accordingly source/drain regions 34will be n-type doped diffusion regions. In other words, the majoritydopant within diffusion regions 34 will be n-type dopant. The term“majority dopant” refers to the dopant that is most abundant within theregions. Accordingly, if both p-type and n-type dopant are present inthe regions, the majority dopant type will be that which is mostprevalent. Additionally, it is noted that the stack 36 (discussed inmore detail below) provided between stacks 22 can be incorporated intoan NMOS transistor if a sufficient threshold voltage is provided.

[0048] The source/drain regions 34 extend under spacers 32 in the shownconstruction. It is to be understood however that other structures canbe formed in which the source/drain regions do not extend underneath thespacers, or even in which at least some of the spacers are eliminated.Additionally, source/drain regions 34 can extend beneath spacers 32 lessthan the full spacer width, can extend the full spacer width or canextend beyond the spacer to beneath the corresponding stack (not shown).

[0049] The various source/drain regions are connected to eithercapacitor constructions 42 or digit lines 44 to define various memorycell units of the DRAM memory array.

[0050] An isolation region 38 extends between transistor constructions14 and 16, and can be utilized to electrically isolate such transistorconstructions from one another. Isolation region 38 comprises stack 36similar to stacks 22 of gate constructions 14 and 16. Stack 36 comprisesthe insulative material 24, conductive mass 28 and insulative cap 34utilized in gate stacks 22. However, in particular embodiments stack 36can differ from gate stacks 22 in having a heavily doped material 40which is differentially doped than the material 26 of stacks 22.

[0051] In particular aspects, material 40 can comprise silicon dopedwith significant concentrations of an opposite type dopant as thatprimarily utilized in source drain regions 34. For instance, ifsource/drain region 34 primarily comprised n-type dopant, material 40can primarily comprise p-type dopant. The utilization of p-type dopantas a majority dopant within doped gate layer 40, while havingsource/drain regions 34 with n-type dopant as majority dopant, can causestack 40 to have a high threshold voltage relative to adjacent devices.This can enable stack 36 to function primarily as an isolation region atparticular threshold voltages utilized to drive adjacent devices, ratherthan as a transistor construction. In some aspects of the invention,material 40 can comprise significant concentrations of both p-type andn-type dopant, and can, for example, comprise concentrations from 1×10¹⁸atoms/cm³ to 5×10²¹ atoms/cm³ of both p-type and n-type dopants.Typically, a concentration of the dopant can be about 1×10²⁰ atoms/cm³.

[0052] In particular embodiments of the present invention, material 40can comprises essentially one type of dopant (i.e. at least 99% of thedopant within material 54 can be p-type) or material 40 can effectivelycomprise two types of dopant (in other words, less than 99% of thedopant within material 40 is p-type). Alternatively, material 40 can bemajority n-doped and coupled to a suitable electrical bias so thatisolation device 38 appropriately functions as a grounded gate.

[0053] If stack 36 is utilized as an isolation region, it can bedescribed as an isolation region having a mass 40 of material extendingbetween a pair of adjacent source/drain regions 34. Further, theadjacent source/drain regions can, as shown, extend the fullspacer-width under spacers 32 associated with stack 36. Alternatively,the adjacent source/drain regions 32 can extend a partial spacer-widthbeneath spacers 32 or can extend under the gate electrode (i.e. canextend under mass 40).

[0054] Stack 36 is shown having conductive layer 28 in contact withother electrical circuitry 48. In embodiments in which stack 36 isutilized as an isolation region, the other circuitry 48 can be anelectrical ground associated with construction 10, or can be slightlypositive or negative relative to ground as long as device 36 does notturn on an underlying channel.

[0055] As a result of the dopant variation within layer 40 (relative tolayers 26 of gate stacks 22) the apparent or effective thickness of gateoxide 24 within stack 36 can change relative to that of stacks 22. Inother words, even though gate oxide 24 has the same physical thicknessin stacks 22 and stack 36, the effective electrical thickness of thegate oxide will be increased in stack 36 relative to stacks 22.

[0056] In particular aspects of the present invention, there is aneffective dopant depletion relative to an interface between gate oxide24 and silicon layer 40. Specifically, silicon layer 40 has a lowereffective concentration of n-type dopant than do silicon layers 26. Suchcan be accomplished by initially providing layer 40 to have the samen-type dopant concentration as do layers 26, and subsequently addingsufficient p-type dopant to layer 40 to alter electrically properties oflayer 40. The p-type dopant concentration can be sufficient to overwhelmthe n-type dopant concentration (i.e. to form the p-type dopant as themajority dopant in layer 40), or alternatively can be sufficient tosimply have a measurable effect on the work function of a transistorconstruction comprising stack 36.

[0057] A doped pocket region 46 can be provided within a semiconductivematerial of substrate 12 beneath isolation structure 38. Doped pocketregion 46 can be doped with a heavy p-type atom such as, for instance,indium. Optionally, doped region 46 can additionally be doped with atleast one other p-type dopant such as, for example, boron. It can beadvantageous to provide indium or other heavy p-type dopant, such as Gaor TI, in the pocket region 46 beneath isolation structure 38 toincrease the threshold voltage of isolation gate 36. Further, indiumwithin pocket region 46 can enhance retention of dopant centrallybeneath isolation device 38. The relatively low diffusivity of indiumcan minimize diffusion of dopant toward the storage node junction andthereby minimize junction leakage. When used in conjunction with anadditional p-type dopant such as, for example, boron, a lower dosage ofthe additional p-type dopant can be utilized relative to concentrationstypically used to minimize charge leakage between nodes across agrounded gate device 38.

[0058] Indium can be provided within pocket region 46 to a concentrationof from about 1×10¹² atoms/cm³ to about 1×10¹³ atoms/cm³. If pocketregion 46 is additionally doped with boron, boron can be provided to aconcentration of from about 1×10¹² atoms/cm³ to about 2×10¹² atoms/cm³.

[0059] Activation of implanted indium can comprise activation by thermalprocessing at a temperature of about 900° C. for between about 1 minuteand about 6 minutes, preferably from about 1 minute to about 2 minutes.Such activation can occur during a reflow of borophosphosilicate glass(BPSG) or can occur in an independent step.

[0060] Doped region 46 preferably has a lateral width that is less thanthe width of gate stack 36. Preferably, pocket region 46 issubstantially centered beneath device 38 and comprises a lateral widththat is less than or equal to the total width of device 38, the totalwidth of device 38 being the furthest distance between outer edges ofthe pair of sidewall spacers 32 associated with gate stack 36. In apreferred configuration, the heavy p-type atom dopant in doped region 46is separated from each neighboring source/drain region 34 by a gap.

[0061] It is noted that in embodiments where boron is implanted intodoped pocket region 46, at least some of the initially implanted boroncan diffuse outwardly from region 46 during activation or other thermalprocessing. In preferred embodiments however, heavy p-type dopantremains substantially within pocket region 46, thereby avoiding highconcentrations of p-type dopant at or near the storage node junctions.Accordingly, the doped pocket region can be referred to as a sub-regionof a doped region.

[0062] Although FIG. 1 shows heavily doped: material 40 of gate stack 36utilized in conjunction with doped channel region 46, the inventionencompasses embodiments wherein material 40 is substituted withalternative conductively doped semiconductor material such as thematerial utilized for layer 26 in gate stacks 22.

[0063] In addition to the features shown in FIG. 1, construction 10 cancomprise doped channel regions within regions of substrate 12 underlyingstacks 22 (not shown). In particular embodiments, doped channel regionsbeneath the transistor devices can be doped with a non-heavy p-typedopant such as, for example boron. Such boron doped channel regions canlack additionally added heavy p-type dopants and can have boronimplanted to a concentration of from about 5×10¹² atoms/cm³ to about9×10¹² atoms/cm³.

[0064] In the shown construction 10, material 40 is physically againstinsulative mass 24, and conductive mass 28 is physically againstmaterial 40. Further, conductive mass 28 can comprise a silicide layerwhich is formed directly on (physically against) layer 40, and canfurther comprise a metal layer, metal compound layer, and/or metal alloylayer which is formed over and physically against the suicide layer.

[0065] Stack 36 can be considered to be within a DRAM array, and thearray can be, for example, a 6 F² or 8 F² array.

[0066] A method of forming the construction of FIG. 1 is described withreferences to FIGS. 2-13. In describing FIGS. 2-13, similar numberingwill be used as was utilized above in describing FIG. 1, as appropriate.

[0067] Referring initially to FIG. 2, wafer construction 10 is shown ata preliminary processing stage. Construction 10 comprises substrate 12,insulative layer 24, and a masking material 102 formed over insulativelayer 24. Masking material 102 can comprise, for example, eitherpositive or negative photoresist, and in particular embodiments cancomprise M108Y™ from JSR™ Corporation of Japan. Referring to FIG. 3,photoresist 102 is photolithographically patterned into a pair ofadjacent and spaced blocks 104 and 106. Block 104 has a sidewall edge105 and a top edge 107. It is to be understood that the term “block” isutilized herein to generically refer to any patterned shape, includingfor example, rectangular shapes, square shapes or shapes with curvededges.

[0068] In the shown embodiment, blocks 104 and 106 are formed inphysical contact with insulative material 24. It is to be understoodthat the invention encompasses other embodiments (not shown) whereinmasking material 102 is formed directly on a semiconductive material ofsubstrate 12 in the absence of insulative layer 24 to result in blocksthat are physically against substrate 12.

[0069] A gap 110 extends between patterned blocks 104 and 106, and inthe shown embodiment an upper surface 112 of insulative material 24 isexposed within gap 110. Patterned blocks 104 and 106 can be consideredto cover a first portion of insulative layer 24, and to leave a secondportion of layer 24 uncovered. In embodiments having material 102 formedin an absence of layer 24 (not shown), patterned blocks 104 and 106 cancover a first portion of substrate 12 and leave a second portion of thesubstrate material uncovered.

[0070] Referring to FIG. 4, a coating 114 is formed over patternedphotoresist blocks 104 and 106, and within gap 110. Coating 114 coversat least some of the portion of insulative material 24 that is exposedbetween blocks 104 and 106, and in the shown embodiment covers all ofthe exposed portion of insulative material 24. Coating 114 is a materialother than photoresist, and in particular applications, corresponds to amaterial designated as AZ R200™ by Clariant International, Ltd. Coating114 is physically against photoresist blocks 104 and 106 and correspondsto a material which can be selectively removed from over exposed portion112 of insulative material 24, while remaining adhered to thephotoresist of blocks 104 and 106.

[0071] In one aspect of the invention, coating 114 corresponds to thematerial designated as AZ R200™, and is coated across an entirety of asemiconductive wafer, and is subsequently spun dry. It is noted that AZR200™ is a water-based material, so it is preferable to conduct theprocedures associated with AZ R200™ in a separate chamber from theprocedures utilized in exposing and developing photoresist, since watercan interfere with standard photoresist processing. Accordingly, apreferred process of the present invention comprises forming aphotoresist mass 102 and photolithographically processing such mass in aseparate “bowl” or chamber from that utilized during formation ofcoating 114.

[0072] After coating 114 is formed, semiconductor construction 10 isbaked at a temperature of from about 100° C. to about 120° C. Suchbaking is thought to diffuse acid from resist 102 into the AZ R200™, andcrosslink the layer of AZ R200™ across resist blocks 104 and 106. Thecrosslinking can bond the coating to blocks 104 and 106 and/or form thecoating into a shell tightly adhered with blocks 104 and 106. Thematerial designated as AZ R200™ is but one material which can beutilized in methodology of the present invention. Other materials whichselectively bond or adhere to photoresist blocks 104 and 106 can be usedalternatively to the material designated as AZ R200™.

[0073] Referring to FIG. 5, coating 114 is exposed to conditions whichselectively remove the coating from between blocks 104 and 106, whileleaving a layer of the coating against blocks 104 and 106. Inapplications in which the coating comprises AZ R200™, such removal canbe accomplished by exposing semiconductor construction 10 to an aqueoussolution comprising surfactant. Such solution can selectively remove anon-crosslinked portion of coating 114. A suitable aqueous surfactantsolution is the material marketed as “SOLUTION C™” by ClariantInternational, Ltd. In applications in which AZ R200™ is utilized,construction 10 can be subjected to a so-called hard bake at atemperature of from about 130° C. to about 140° C. after removal of thenon-crosslinked material. Such hard bake can fully dry and furthercrosslink the portions of coating 114 remaining around blocks 104 and106.

[0074] The coating 114 remaining around a photoresist block can beconsidered to define a second block which extends laterally outwardbeyond edges of the photoresist block. Specifically, the coating 114over photoresist block 104 defines lateral edge 116 which extendslaterally outward beyond lateral edge 105 of block 104, and also definesa top edge 115 which extends elevationally above the top edge 107 ofblock 104. Similarly, the coating 114 around block 106 comprises alateral edge 119 which extends laterally outward beyond the lateral edge109 of block 106, and further comprises a top edge 117 which iselevationally above the top edge 111 of block 106.

[0075] Photoresist block 104 and the coating 114 surrounding suchphotoresist block together define a masking block which is enlarged andlaterally wider than was photoresist block 104. Also, photoresist block106 and the coating 114 surrounding such photoresist block togetherdefine a masking block 120 which is enlarged and laterally wider thanphotoresist block 106. Masking blocks 118 and 120 (also referred to asenlarged blocks) have a narrower gap between them than did photoresistblocks 104 and 106. In other words coating 114 narrows gap 110 to reducea dimension of such gap.

[0076] Referring to FIG. 6, a dopant 122 is implanted relative toconstruction 10. Masking blocks 118 and 120 prevent the dopant frombeing implanted into the blocked regions of construction 10. Theunblocked region corresponds to a region within a surface area wherestack 36 (FIG. 1) is ultimately to be formed. Implanting dopant 122forms a doped pocket region 46 as shown in FIG. 7. Doped pocket region46 has a width corresponding to the narrowed width of gap 110.

[0077] Referring again to FIG. 6, dopant 122 can comprise a single heavyp-type dopant such as indium or can comprise both a heavy p-type dopantand an additional p-type dopant such as, for example, boron. AlthoughFIGS. 6 and 7 depict formation of doped pocket region 46 as utilizing asingle doping step, it is to be understood that the present inventionencompasses alternative embodiments (not shown), wherein two or moreimplanting steps are utilized to implant dopant into region 46. Forexample, a non-heavy p-type dopant such as boron for example can beimplanted into exposed region 112 (FIG. 3) prior to forming coatinglayer 114 over photoresist blocks 104 and 106. Alternatively, a seconddopant can be implanted after formation of enlarged blocks 118 and 120but in an independent step either prior to or subsequent to doping withthe heavy p-type dopant.

[0078] Dopant 122 can be activated by thermal processing at atemperature of from about 900° C. for about 1 minute to about 6 minutes,preferably from about 1 minute to about 2 minutes. Activation of dopant122 can occur during reflow of BPSG or in an independent step.

[0079] Referring to FIG. 8, materials 102 and 114 (FIG. 5) are removedfrom over substrate 12.

[0080] The present invention can advantageously form doped pocketregions that are narrower than can be accomplished utilizingphotolithographic processing alone. Specifically, if photoresist blocks104 and 106 (FIG. 3) are considered to be as close to one another as ispossible by a particular photolithographic patterning process, thenprocessing of the present invention has effectively defined new maskingblocks 118 and 120 (FIG. 5) which are closer together than could beachieved by photolithographic processing alone. In other words, if gap110 was initially formed to have a minimum feature size achievable byphotolithographic processing, then the formation of coating 114 haseffectively reduced the feature size of gap 110 to below the minimumachievable feature size. In particular embodiments, the reduced width ofgap 110 between blocks 118 and 120 can be less than or equal to abouthalf the width of gap 110 between blocks 104 and 106 prior to theformation of coating 114.

[0081] In embodiments wherein layer 102 was formed over substrate 12 inan absence of insulative material 24 (not shown), such insulative layercan be formed after the removal of materials 102 and 114 prior tosubsequent processing.

[0082] In embodiments of the invention having doped channel regions (notshown) underlying gate stacks 22 (FIG. 1) wherein the channel regionsare doped only with non-heavy p-type dopants, such channel regions canbe formed by implanting dopant into the appropriate areas of thesubstrate after removal of materials 102 and 114. Alternatively, suchchannels can be formed prior to formation of layer 102. Formation ofsuch channel regions can comprise implanting boron to a concentration offrom about 5×10¹² atoms/cm³ to about 9×10¹² atoms/cm³ .

[0083] Referring to FIG. 9, mass 124 is formed over insulative layer 24.Mass 124 can be undoped as initially deposited, or alternatively can bein situ doped. In the shown application, mass 124 is undoped, andaccordingly has not acquired the properties of either mass 26 (FIG. 1),or mass 40 (FIG. 1).

[0084] A patterned masking material 126 is formed over mass 124, andsuch blocks portions of mass 124. Masking material 126 can comprise, forexample, photoresist and can be formed into the shown pattern by, forexample, photolithographic processing. Masking material 126 covers aportion of construction 10 where stack 36 is ultimately to be formedwhile leaving other portions of construction 10 uncovered.

[0085] Referring to FIG. 10, a dopant 127 is implanted into construction10, and specifically is implanted into portions of material 124 (FIG. 9)which are not covered by mask 126. Such converts the material 124 tomaterial 26. Dopant 127 can comprise, for example, n-type dopant (suchas phosphorous or arsenic). Dopant 127 can be provided to aconcentration of at least 1×10²⁰ atoms/cm³, and typically is provided toa concentration of from about 1×10²⁰ atoms/cm³ to about 5×10²¹atoms/cm³.

[0086] Referring to FIG. 11, masking material 126 is removed andreplaced by another patterned masking material 128. Masking material 128can comprise, for example, photoresist and can be formed into the shownpattern by, for example, photolithographic processing. Masking material128 covers some portion of construction 110 while leaving a portionwhere stack 36 is ultimately to be formed uncovered.

[0087] A dopant 129 is implanted into construction 10, and specificallyis implanted into portions of material 124 (FIG. 9) which are notcovered by mask 128. Such converts the material to material 40. Dopant129 can comprise an opposite conductivity type relative to dopant 127.Further, dopant 129 can be implanted to a concentration greater than1×10²⁰ atoms/cm³.

[0088] In particular applications mask 126 (FIG. 9) can be eliminated,and dopant 127 implanted into an entirety of material 124 (FIG. 9).Subsequently, mask 128 can be formed and dopant 129 implanted at aconcentration higher than that of dopant 127. The dopant 129 can theneffectively overwhelm the dopant 127 within exposed (unblocked) regionof construction 10 to form doped materials 40 and 26.

[0089] Referring to FIG. 12, masking material 128 (FIG. 11) is removed.Layers 28 and 30 are formed across: construction 10. As discussed above,layer 28 can comprise silicide, metal, metal compounds and/or metalalloys; and layer 30 can comprise an insulative material such as, forexample, silicon dioxide and/or silicon nitride.

[0090] Referring to FIG. 13, stacks 22 and 36 are patterned from thelayers 24, 26, 28, 30 and 40 of FIG. 12. Such patterning can beaccomplished by, for example, forming a patterned photoresist mask (notshown) over the layers, and subsequently transferring a pattern from themask through the layers utilizing suitable etching conditions.

[0091] The stacks 22 and 36 can be incorporated into the constructionsof FIG. 1 by forming source/drain regions 34 (shown in FIG. 1) withinsubstrate 12, and forming sidewall spacers 32 (shown in FIG. 1).Source/drain regions 34 preferably can be formed to extend beneathsidewall spacers 32 of the of the corresponding transistor device 14 and16 or isolation device 38, without extending beneath the correspondingstack 22 or 36.

[0092] Another application of the invention is described with referenceto FIGS. 14-20. Similar numbering will be utilized in describing FIGS.14-20 as was used above in describing FIGS. 1-13 where appropriate.

[0093] Construction 10 shown in FIG. 14 can comprise all of the featuresshown in FIG. 1, and can additionally comprise one or both of channelpocket implants 45 and 47 within channel regions underlying transistorgate stacks 22. Channel pocket regions 45 and 47 can comprise implantsof heavy p-type atoms such as, for example, indium. In particularembodiments, doped pocket regions 45 and 47 and the correspondingsurrounding channel area can be additionally doped with a second p-typedopant such as, for example, boron. It can be advantageous to utilizeindium pocket implants within a boron doped channel region of transistordevices to decrease the concentration of boron utilized in the channelregion. For example, in embodiments of the present invention whereinchannel pocket regions 45 and 47 are implanted to an indiumconcentration of from about 1×10¹² atoms/cm³ to about 1×10¹³ atoms/cm³,the boron dose utilized in the channel region can be from about 1×10¹²atoms/cm³ to about 2×10¹² atoms/cm³ relative to typical boron dosed offrom about 5×10¹² atoms/cm³ to about 1×10¹³ atoms/cm³ that are utilizedin channel regions in the absence of the channel pockets 45 and 47 ofthe present invention.

[0094] A method for forming the construction of FIG. 14 is describedwith reference to FIGS. 15-20. In general, the methods utilized informing the construction shown in FIG. 14 can be as described above inreference to formation of the FIG. 1 construction, combined with thefollowing alternative processing steps. Referring initially to FIG. 15,wafer construction 10 is shown at an alternative processing stagesubsequent to FIG. 2. Masking material 102 (FIG. 2) can be patternedutilizing suitable photolithographic processes to form spaced blocks203, 204, 206 and 208. Gaps 210 extend between patterned blocks 203 and204, between patterned blocks 204 and 206, and between patterned blocks206 and 208. In the shown embodiment, an upper surface 212 of insulativelayer 24 is exposed within gaps 210. Alternatively, patterned blocks203, 204, 206 and 208 can be formed in the absence of layer 24 (notshown) and upper surface 212 can comprise a semiconductive material ofsubstrate 12.

[0095] Referring to FIG. 16, coating 114 is formed over patternedphotoresist blocks 203, 204, 206 and 208, and within gaps 210. Asdiscussed above, coating 114 can be selectively removed from between thepatterned photoresist blocks thereby forming the narrowed gaps 210 asshown in FIG. 17. In particular embodiments, narrowed gaps 210 cancomprise a width that is less than or equal to about half the width ofthe gaps prior to formation of coating 114. As additionally shown inFIG. 17, selective removal of coating 114 can form enlarged blocks 218,219, 220 and 221.

[0096] Referring to FIG. 18, a dopant 122 is implanted into construction10, and specifically is implanted into portions of substrate 12 whichare not covered by mask blocks 218, 219, 220 and 221.

[0097] Referring to FIG. 19, dopant 122 (FIG. 18) is implanted to formchannel pocket regions 45 and 47, and pocket region 46. Such pocketregions have a width corresponding to the width of narrowed gap 210. Asdiscussed above, dopant 122 can comprise indium and in particularembodiments can additionally comprise an additional p-type dopant suchas, for example, boron. Accordingly, pocket regions 45, 46 and 47 can beimplanted with indium in the absence of additional dopants or cansimultaneously be implanted with both indium and, for example, boron.Doped pocket region 46 corresponds to a region of the substrate whichwill eventually underlie isolation device 38 (FIG. 14). Doped channelpocket region 45 is substantially centrally located within a channelregion that will eventually be associated with transistor device 14(FIG. 14). Similarly, channel pocket region 47 corresponds to asubstantially centered sub-region within a channel region that willeventually underlie transistor device 16 (FIG. 14).

[0098] It is noted that boron and/or other dopants can be implanted intoat least one of the channel regions that will underlie devices 14 and16, or the corresponding region beneath isolation device 38, in anindependent doping step that is independent from implanting dopant 122.Such independent step can occur prior to formation of resist blocks 203,204, 206 and 208 (FIG. 15) or can occur after formation of the patternedresist blocks but prior to formation of enlarged blocks 218, 219, 220and 221 (FIG. 17). Alternatively, the independent doping can occur afterformation of enlarged masking blocks 218, 219, 220 and 221 in anindependent step prior to or subsequent to indium implant 122.

[0099] Activation of indium can comprise heat processing as describedabove. Preferably, indium diffusion from the pocket region into thesurrounding substrate is minimized. In embodiments having boronadditionally implanted, indium doped pockets 45 and 47 can besub-regions of larger channel regions formed by boron diffusion. Inpreferred embodiments, the doped pockets 45, 46, and 47 remain narrowerthan width of the overlying stack. In particular embodiments, the widthof the pockets will remain about the width of narrowed gap.

[0100] Referring to FIG. 20, masking blocks 218, 219, 220 and 221 areremoved from over substrate 112. Semiconductor construction 10, as shownin FIG. 20, can then be processed as discussed above (FIGS. 10-13 andcorresponding text) to form the constructions shown in FIG. 14. It canbe advantageous to provide indium within channel pocket regionsassociated with transistor devices to allow a lower concentration ofboron or other p-type dopant to be utilized in the channel region,thereby decreasing the amount of dopant that can diffuse toward thestorage node junction. High concentrations of p-type dopants at orsurrounding a storage node junction can increase charge leakage.Accordingly, decreasing an amount of high diffusivity dopant such as,for example, boron, utilized in the channel region can assist indecreasing leakage.

[0101]FIG. 21 shows an alternative semiconductor construction 10 thatcan be formed utilizing methods of the present invention. Theconstruction shown in FIG. 21 can be identical to the construction shownin FIG. 14 with an exception being the absence of the pocket implantregion underlying isolation device 38. Although FIG. 21 depicts acomplete absence of pocket implant beneath the isolation device, theinvention encompasses constructions having a pocket lightly doped withindium (i.e. less than about 1×10¹² atoms/cm³, not shown). Inconstructions of the present invention having a lightly doped indiumpocket or an absence of doped pocket beneath isolation device 38, theisolation device can comprise a majority p-type doped layer 40(discussed above). As will be understood by those of ordinary skill inthe art, construction 10 of FIG. 21 can be formed utilizing the methodsdiscussed with reference to FIGS. 15-20 above combined with alternativephotolithographic patterning of the masking material 102 (FIG. 2). Suchalternate patterning can expose regions of the substrate correspondingto the eventual location of transistor devices 14 and 16 while coveringother areas of the substrate, including the area that will eventuallyunderlie isolation device 38.

[0102]FIG. 22 illustrates a semiconductor construction 10 encompassed byanother aspect of the present invention. Construction 10, as shown inFIG. 22, can be formed by optional processing steps in addition to thosedescribed with reference to forming the construction shown in FIG. 14.As shown in FIG. 22, at least some of the source/drain regions 34present in construction 10 can comprise extension regions 50, 52 whichcan extend the associated source/drain region farther beneath anassociated gate device 14, 16. Extension regions 50 and 52 can extendthe associated source/drain region 34 such that the source drain regionextends the full width of an overlying spacer 32. Alternatively, theextensions can extend the source/drain region to less than the fullspacer width beneath the corresponding device, or can extend thesource/drain region partially beneath gate stack 22.

[0103] In particular embodiments, source/drain regions 34 can bemajority doped with n-type dopant, and extension regions 50 and 52 canbe majority doped with a p-type dopant. In preferred embodiments,extensions 50 and 52 can comprise a heavy p-type dopant such as, forexample, indium. An appropriate indium concentration within theextensions can be from about 1×10¹² atoms/cm² to about 3×10¹² atoms/cm².

[0104] As shown in FIG. 22, semiconductor construction 10 comprisingsource/drain extensions 50, 52 can be formed to have such extensionsbeneath only one of the pair of sidewalls 32 associated with a givenstack 22. In other words, extension implants 50, 52 can be provided on asingle side of a corresponding transistor device 14, 16. Preferably, asshown in FIG. 22, extensions 50 and 52 are provided only on bit contactsides of gates 14 and 26 and are absent from the source/drain region onthe opposing storage node sides of the gates. It can be advantageous toutilize indium implant extensions of source/drain regions associatedwith bit contact sides of transistor devices 14 and 16 to allow areduction in the amount of indium utilized in channel pocket implants 45and 47. In the presence of extensions 50 and 52, pocket channel regions45 and 47 can comprise an indium concentration of from about 2×10¹²atoms/cm² to about 5×10¹² atoms/cm² and can additionally comprise boronat the concentrations set forth above with respect to the semiconductorconstruction shown in FIG. 14.

[0105] A method of forming the construction of FIG. 22 is described withreference to FIGS. 23-24. Referring to FIG. 23, such illustrates furtherprocessing of a construction similar to that shown in FIG. 14 prior toconnection to any capacitor construction or digit lines. A maskingmaterial 174 is formed over construction 10 and is patterned to exposeportions of the substrate on what will be future bit line contact sidesof transistor devices 14 and 16. Masking material 174 can comprise, forexample, photoresist; and can be patterned utilizing suitablephotolithographic processes.

[0106] A dopant 176 is implanted relative to construction 10 and formsextension regions 50 and 52 shown in FIG. 24. Dopant 176 can beimplanted using angled implant techniques typically utilized for forminghalo implants relative to a gate. Implant regions 50 and 52 differ fromtypical halo implants, however, in that implants 50 and 52 do not form aring shaped structure since dopant is implanted only on one side of thecorresponding gate, the opposing side of the gate being blocked bymasking material 174. Dopant 176 can comprise a p-type dopant andpreferably comprises a heavy p-type dopant such as indium.

[0107] The semiconductor construction shown in FIG. 24 can be furtherprocessed to remove photoresist material 174 and to form theconstruction shown in FIG. 22.

[0108]FIG. 25 illustrates a semiconductor construction 10 encompassed byanother aspect of the present invention and will be described usingsimilar numbering as was used above in FIGS. 1-24 where appropriate. Theconstruction 10 shown in FIG. 25 is similar to the constructionillustrated in FIG. 22 with an exception being the presence of a shallowtrench isolation region 54 in place of the isolation device 38 (FIG.14).

[0109] As will be understood by those skilled in the art, construction10 as shown in FIG. 25 can be formed utilizing conventional shallowtrench isolation region formation combined with various methods of thepresent invention described above. Shallow trench region 54 can beformed at an initial processing step prior to formation of patternablematerial 102 (FIG. 2). Material 102 can then be patterned by methodsdiscussed above to expose the regions of substrate while leaving otherregions covered. Coating material 144 can be formed and processed toexpose regions that will eventually underlie central portions of stacks22 while other regions, including the shallow trench isolation region,remain masked. Channel pockets 45 and 47 can then be formed as describedabove, followed by formation of the additional features shown in FIG.25.

[0110] Although FIGS. 22 and 25 show implant extensions 50 and 52 beingutilized in conjunction with channel pocket regions 45 and 47, it is tobe understood that the invention encompasses embodiments whereinextensions 50 and 52 are utilized in semiconductor constructions in anabsence of the described pocket regions 45 and 47.

[0111] In addition to the above described embodiments, the inventionincludes damascene processes for forming gate constructions. Anexemplary method of forming a construction utilizing a damascene processis described with reference to FIGS. 26-29.

[0112] Referring to FIG. 26, an initial step can comprise depositing alayer of dielectric material 202 over insulative material 24.Alternatively, dielectric layer 202 can be deposited on substrate 12 inan absence of an insulative layer and insulative material 24 can begrown after the damascene process. Source-drain regions 34 can bepresent prior to depositing dielectric layer 202 as shown in FIG. 26, orcan be formed during or after gate formation.

[0113] Dielectric material 202 can be patterned by conventional methods,such as photolithography, to form patterned blocks 203 and 205, theblocks having sidewalls 204 and 206 being separated by a gap. Removablespacers 208 can be formed along sidewalls 204 and 206. Removable spacers208 can be formed for example, by depositing a layer of sacrificialmaterial and anisotropically etching the sacrificial material. Spacers208 have lateral edges 209 and 211 that are separated by a narrowed gaprelative to the distance between sidewalls 204 and 206. A dopant 122(discussed above) is implanted relative to construction 10 to form adoped pocket region 212 as shown in FIG. 27. Doped pocket region 212 hasa width corresponding to the width between lateral edges 209 and 211.

[0114] Referring to FIG. 27, spacers 208 are removed and a layer ofpolysilicon 214 is conformally deposited over construction 10 and alongsidewalls 204 and 206. A gate electrode material 216, such as WN/W orother compositions comprising a metal and/or metal nitride, can bedeposited over polysilicon layer as shown in FIG. 28.

[0115] Referring to FIG. 29, a planarization step utilizing for examplechemical mechanical polishing is performed to form the planarized gatestructure having a metal gate electrode 220 as shown. The gate structurecan have a gate structure width corresponding to the distance betweenthe sidewalls 204 and 206. Accordingly, doped pocket region 212 can havea width that is less than the width of the gate structure and inparticular embodiments, pocket region 112 can comprise a width less thanor equal to about half the width of the gate structure.

[0116] A channel region which underlies the damascene gate structure andsurrounding pocket (shown in FIG. 29) region can additionally compriseboron as discussed above relative to gate stack structures 22 and 36.Source-rain extensions (not shown) can be utilized in conjunction withthe gate and can be formed as described above.

[0117] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor construction comprising: a pair of gate structuressupported by a semiconductive material; and an isolation region betweenthe pair of gate structures, the isolation region comprising: an indiumdoped pocket within the semiconductive material, the pocket regioncomprising a first width; and a third gate structure over the pocketregion, the third gate structure comprising a gate stack having alateral width that is greater than the first width.
 2. The semiconductorstructure of claim 1 wherein the pocket region comprises an indiumconcentration from about 1×10¹² atoms/cm³ to about 1×10¹³ atoms/cm³. 3.The semiconductor construction of claim 1 further comprising a pair ofsource/drain regions that extend partially under the third gatestructure, the source/drain regions being majority doped with an n-typedopant and wherein the gate stack of third gate structure comprises alayer of conductively doped material majority doped with a p-typedopant.
 4. The semiconductor construction of claim 3 wherein theconductively doped material comprises at least 1×10¹⁸ atoms/cm³ n-typedopant and at least 1×10¹⁸ atoms/cm³ p-type dopant.
 5. The semiconductorconstruction of claim 1 wherein the pair of gate structures comprise apair of transistors having transistor stacks, each of the transistorstacks having a transistor stack width, wherein each of the transistorsis disposed over a channel region defined within the semiconductivematerial, each channel region comprising an indium doped channel pockethaving a pocket width that is less than the transistor stack width. 6.The semiconductor construction of claim 5 wherein the channel regionsare additionally doped with from about 1×10¹² atoms/cm³ to about 2×10¹²atoms/cm³ boron.
 7. The semiconductor construction of claim 1 whereineach of the pair of gate structures comprises: a layer of polysilicon;and a metal material over the layer of polysilicon, the metal materialhaving a planarized upper surface.
 8. A semiconductor constructioncomprising: a pair of gate structures supported by a semiconductivematerial; and an isolation region between the pair of gate structures,the isolation region comprising an indium doped pocket within thesemiconductive material.
 9. The semiconductor construction of claim 8wherein each of the pair of gate structures comprises a layer comprisingtungsten.
 10. A semiconductor construction comprising: a pair of channelregions a within a semiconductive material, at least a portion of eachof the channel regions being an indium doped sub-region, each indiumdoped sub-region having a first width; and a pair of transistorconstructions separated by an isolation region which isolates thetransistor constructions from one another, each transistor constructionbeing disposed over a channel region comprised by the pair of channelregions, each of the transistor constructions comprising a transistorgate having a second width that is greater than the first width, each ofthe gates being substantially laterally centered over the correspondingchannel region.
 11. The semiconductor structure of claim 10 wherein theisolation region comprises a shallow trench isolation region.
 12. Thesemiconductor structure of claim 10 wherein the isolation regioncomprises an isolation gate having a first conductively-doped materialseparated from a second conductively-doped material by an interveninginsulative material; the first conductively doped material comprises ap-type majority dopant, and further comprising a lack of indium dopedpocket beneath the isolation gate.
 13. The semiconductor structure ofclaim 10 wherein the isolation region comprises an isolation gate, andfurther comprising a doped pocket region disposed in the substrateunderlying the isolation gate and being substantially laterally centeredrelative to the isolation gate.
 14. The semiconductor substrate of claim13 wherein the doped pocket region is lightly doped with indium andwherein the isolation gate comprises a first conductively-doped materialseparated from a second conductively-doped material by an interveninginsulative material; and wherein a majority dopant in the firstconductively doped material is p-type.
 15. The semiconductor substrateof claim 13 wherein at least part of the doped pocket region is indiumdoped.
 16. A semiconductor construction comprising: a field effecttransistor having an access side and an opposing bitline side; a pair ofsource/drain regions associated with the field effect transistor; one ofthe source/drain regions being on the access side and the othersource/drain region being on the bitline side of the field effecttransistor device; and an indium implant associated with only one of thepair of source/drain regions.
 17. The semiconductor construction ofclaim 16 wherein the indium implant is associated with the source/drainregion on the bitline side of the field effect transistor.
 18. Asemiconductor construction comprising: a semiconductor substrate a pairof conductively doped diffusion regions within a semiconductive materialof the substrate, the conductively doped diffusion regions comprising afirst type of dopant; a transistor construction over the substrate, thetransistor construction comprising: a gate disposed between the pair ofdiffusion regions and having a pair of opposing sidewalls; spacersdisposed along the opposing sidewalls, the conductively doped diffusionregions extending under the spacers; and a diffusion region extensionpresent on a first side of the transistor construction and absent on anopposing second side of the transistor construction, the diffusionregion extension comprising a second type of dopant and extending thediffusion region farther beneath the transistor construction on thefirst side of the transistor construction relative to the diffusionregion on the second side of the transistor construction.
 19. Thesemiconductor construction of claim 18 wherein the first type of dopantis an n-type and the second type dopant is a p-type.
 20. Thesemiconductor construction of claim 18 wherein the second type dopant isindium.
 21. The semiconductor construction of claim 18 wherein thediffusion region comprising the diffusion region extension is associatedwith a bitline contact.
 22. A semiconductor construction comprising: asemiconductive material substrate; a first and a second transistorconstruction over the semiconductive substrate material, each of thefirst and second transistor constructions having opposing sidewalls witha pair of insulative spacers along the sidewalls; a first and a secondsource/drain region within the substrate, the first transistorconstruction being disposed between the first and the secondsource/drain regions, a first end of the first source/drain regionextending beneath the spacer on a first side of the first transistorconstruction and the second source/drain region extending beneath thespacer on an opposing second side of the first transistor construction;a third and a fourth source/drain region within the substrate, thesecond transistor construction being disposed between the third andfourth source/drain regions, a first side of the fourth source/drainregion extending beneath the spacer on a first side of the secondtransistor construction, and the third source/drain region extendingbeneath the spacer on an opposing second side of the second transistorconstruction; the first, second, third and fourth source/drain regionsbeing commonly doped with a first type of dopant; a source/drainextension associated with the first side of the first source/drainregion, the source/drain extension being doped with a second type ofdopant and extending the first side of the first source/drain regionfarther beneath the first transistor construction; extensions beingabsent from a second side of the first source/drain region, and absentfrom the second source/drain region.
 23. The semiconductor constructionof claim 22 further comprising channel regions defined within thesubstrate beneath each of the first and second transistor constructionsat least a portion of the channel regions being doped with indium. 24.The semiconductor construction of claim 22 further comprising asource/drain extension associated with the first side of the fourthsource/drain region, the source/drain extension being doped with asecond type of dopant and extending the first side of the fourthsource/drain region farther beneath the second transistor construction;extensions being absent from a second side of the fourth source/drainregion, and absent from the third source/drain region.
 25. Thesemiconductor construction of claim 22 further comprising an isolationstructure between the first and second transistor constructions.
 26. Thesemiconductor construction of claim 25 further comprising a doped pocketregion within the semiconductive material beneath the isolationstructure, at least a portion of the pocket region being doped withindium.
 27. The semiconductor construction of claim 25 wherein theisolation structure comprises a first conductively-doped materialseparated from a second conductively-doped material by an interveninginsulative material; the first conductively-doped material being dopedto at least 1×10¹⁸ atoms/cm³ with n-type dopant and to at least 1×10¹⁸atoms/cm³ with p-type dopant.
 28. The semiconductor construction ofclaim 27 wherein a majority dopant in the first conductively dopedmaterial is p-type.
 29. The semiconductor construction of claim 28having an absence of any indium implant beneath the isolation structure.30. The semiconductor construction of claim 28 having a lightly dopedindium implant beneath the isolation structure.
 31. The semiconductorconstruction of claim 22 further comprising a shallow trench isolationregion between the first and the second transistor constructions.
 32. ADRAM construction comprising: a first and a second gate structure; fournodes, the four nodes comprising a first node, a second node, a thirdnode and a fourth node, the first node being in gated electricalconnection with the second node through the first gate structure, andthe third node location being in gated electrical connection with thefourth node location through the second gate structure; each of the fournodes having a diffusion region associated therewith, the diffusionregions associated with the first and second nodes each extending underthe first gate structure, and the diffusion regions associated with thethird and fourth nodes extending under the second gate structure; anisolation region between the second and third nodes, the isolationregion electrically isolating the first and the second gate structuresfrom one another; a bit line contact in electrical connection with thefirst node; a capacitor construction in electrical connection with thesecond node, the capacitor construction comprising a storage node; anindium implant in the diffusion region associated with the first node,the implant being under the first gate structure proximate the firstnode; and an absence of an indium implant in the diffusion regionassociated with the second node.
 33. The DRAM construction of claim 32wherein the indium implant is a first indium implant and furthercomprising: a second indium implant, the second indium implant being inthe diffusion region associated with the fourth node and under thesecond gate, wherein the fourth node is in electrical connection with abitline contact; and an absence of an indium implant associated with thediffusion region associated with the third node.
 34. The DRAMconstruction of claim 32 wherein the isolation region comprises anisolation structure having a total width, and further comprising a dopedpocket beneath the isolation structure, the doped pocket comprising awidth that is less than or equal to about half a total width of theisolation structure.
 35. The DRAM construction of claim 32 wherein eachof the gate structures comprises opposing gate sidewalls and a pair ofinsulative spacers having inside surfaces along and against the gatesidewalls and having outside surfaces away from the sidewalls, each gatestructure comprising a total width corresponding to the greatestdistance between the outside surfaces of the pair of insulative spacersassociated with the corresponding gate; and wherein the DRAMconstruction further comprises conductively doped channel regionsbeneath each of the gate structures, at least a portion of the channelregions being doped with indium, the portion comprising a width that isless than or equal to about half the total width of the gate structure.36. A method of forming a doped region in a semiconductor substratecomprising: forming a pair of blocks over a semiconductive material of asemiconductor substrate, the pair of blocks being spaced from each otherby a gap comprising a first distance; narrowing the gap; and implantingdopant into the semiconductive material though the narrowed gap to forma doped region in the semiconductive material.
 37. The method of claim36 wherein the blocks comprise patterned photoresist and having opposingsidewalls, and wherein the narrowing the gap comprises: forming acoating over the patterned photoresist and over the substrate within thegap; and selectively removing the coating from over at least a portionof the substrate within the gap while leaving the coating on thephotoresist block, the coating material forming sidewall extensionsagainst the opposing sidewalls.
 38. The method of claim 36 wherein theimplanting dopant through the narrowed gap comprises implanting indiumto a concentration of from about 1×10¹² atoms/cm³ to about 1×10¹³atoms/cm³.
 39. The method of claim 36 wherein the implanting dopantthrough the narrowed gap comprises implanting boron to a concentrationof from about 1×10¹² atoms/cm³ to about 2×10¹² atoms/cm³, and implantingindium to a concentration of from about 1×10¹² atoms/cm³ to about1×10¹³atoms/cm³.
 40. The method of claim 36 wherein the implantingdopant through the narrowed gap comprises implanting a second dopant,the method further comprising implanting a first dopant into thesemiconductive material prior to implanting the second dopant.
 41. Themethod of claim 40 wherein the first dopant comprises boron and thesecond dopant comprises indium.
 42. The method of claim 40 wherein theimplanting the first dopant occurs prior to extending the blocks. 43.The method of claim 40 wherein the implanting the first dopant occursduring the narrowing the gap.
 44. The method of claim 36 furthercomprising activating the dopant at a temperature of about 900° C. forbetween about 1 minute to about 6 minutes.
 45. A method of forming asemiconductor construction, comprising: forming a layer of patternablematerial over a semiconductive substrate material; patterning the layerof patternable material to form at least two patterned blocks, a pair ofadjacent blocks being separated by a first gap; forming a coating overthe pair of adjacent blocks and across the first gap between theadjacent blocks; selectively removing the coating from across the firstgap while leaving the coating on the pair of adjacent blocks; the pairof blocks and coating together defining a pair of enlarged blocks thatare separated by a second gap; the second gap being narrower than thefirst gap; while the enlarged blocks remain over the semiconductivesubstrate material, implanting at least one dopant within thesemiconductive material within the second gap to form a doped region;and removing the enlarged blocks from over the semiconductive substratematerial.
 46. The method of claim 45 wherein the patternable materialcomprises photoresist and wherein the coating comprises a material whichcross-links when exposed to the acid from the photoresist.
 47. Themethod of claim 45 wherein the coating corresponds to a materialdesignated as AZ R200™ by Clariant International, Ltd.
 48. The method ofclaim 45 wherein the patterned blocks are formed by a photolithographicprocess; wherein the photolithographic process is limited to a minimumfeature size that can be obtained by the photolithographic process, thefirst gap corresponding to about the minimum feature size; and whereinthe doped region of the semiconductive material formed by the implantinghas a region width that is less than the minimum feature size.
 49. Themethod of claim 48 wherein the region width is less than or equal toabout 50% of the minimum feature size.
 50. The method of claim 45further comprising: forming a first source/drain region and a secondsource/drain region within the semiconductive substrate-material, thefirst source/drain region being laterally spaced from a first edge ofthe doped region and the second source/drain region being laterallyspaced from a second opposing edge of the doped region; and forming anisolation mass over the doped region, the first and second source/drainregions extending partially under the isolation mass.
 51. The method ofclaim 50 wherein the isolation mass comprises a gate stack, the gatestack comprising a layer of conductively doped material separated fromthe doped region by an insulative material layer, the layer ofconductively doped material being majority doped with a p-type dopant,and wherein the source/drain regions are majority doped with an n-typedopant.
 52. The method of claim 50 further comprising forming a pair oftransistor devices over the semiconductor substrate, the transistordevices being electrically isolated from one another by the isolationmass.
 53. A DRAM forming method comprising: forming a first wordline anda second wordline over a substrate, each wordline comprising a pair ofopposing sidewalls; defining four nodes proximate the wordlines, thefour nodes comprising a first node, second node, third node and fourthnode, the second node being in gated electrical connection with thefirst node through the first wordline, and the fourth node being ingated electrical connection with the third node through the secondwordline; defining a first, second, third and fourth diffusion regions,the first diffusion region being associated with the first node, thesecond diffusion region being associated with the second node, the thirddiffusion region being associated with the third node, and the fourthdiffusion region being associated with the fourth node; defining anisolation region between the first wordline and the second wordline, theisolation region electrically isolating the first and second wordlinesfrom each other; forming a pair of spacers along opposing sidewalls ofeach wordline; the first and second diffusion regions extending aninitial distance under the first wordline, and the third and fourthdiffusion regions extending an initial distance under the secondwordline; and extending the first diffusion region farther under thefirst wordline relative to the initial distance without extending thesecond diffusion region.
 54. The method of claim 53 further comprisingextending the fourth diffusion region farther under the second wordlinerelative to the initial distance without extending the third diffusionregion.
 55. The method of claim 53 wherein the spacers comprise a spacerwidth and wherein the initial distance is less than the spacer width.56. The method of claim 53 wherein each of the diffusion regions areconductively doped with a first type dopant and wherein the extendingcomprises halo implanting a second type dopant.
 57. The method of claim53 wherein the diffusion regions are majority doped with n-type dopantand wherein the extending comprises forming extension regions majoritydoped with p-type dopant.
 58. The method of claim 53 wherein theisolation region comprises a shallow trench isolation region.
 59. Themethod of claim 53 further comprising: forming a first and secondcapacitor constructions; the first capacitor construction being inelectrical connection with the second node, and the second capacitorconstruction being in electrical connection with the third node;andforming a first bit line contact in electrical connection with the firstnode and a second bit line contact in electrical connection with thethird node.
 60. The method of claim 53 wherein the defining an isolationregion comprises: forming a doped pocket region within the semiconductorsubstrate, the doped pocket region comprising a pocket width; andforming an isolation mass over the substrate and over the pocket region,the isolation mass having a total mass width that is greater than thepocket width.
 61. The method of claim 60 wherein the isolation masscomprises: a gate stack over the substrate, the gate stack havingopposing sidewalls; a pair of insulative spacers along the opposingsidewalls, the total mass width being a distance between outer edges ofthe pair of insulative spacers measured at a surface of the substrate;and wherein the total mass width is at least about double the pocketwidth.
 62. A method of forming a semiconductor construction, comprising:forming a dielectric material over a semiconductive substrate material;patterning the dielectric material to form at least two patternedblocks, a pair of adjacent blocks being separated by a first gap, eachblock having a sidewall within the first gap; forming a pair of spacersalong the sidewalls and within the first gap, the spacers having lateraledges separated by a gap, the second gap being narrower than the firstgap; while the spacers remain along the sidewalls, implanting at leastone dopant into the semiconductive material within the second gap toform a doped region; and removing the spacers from along the sidewalls.63. The method of claim 62 further comprising after removing thespacers, forming a layer of polysilicon over the semiconductive materialwithin the gap and along the sidewalls.
 64. The method of claim 63further comprising: depositing a material comprising at least one of ametal and a metal nitride over the polysilicon layer; and planarizingthe material.